1. Field of the Invention
The present invention relates generally to semiconductor fabrication, and more particularly to a method for forming and locating a doped region, referred to as a buried layer, under an overlying epitaxial layer.
2. Description of the Prior Art
Integrated circuits are fabricated by forming a large number of discrete devices on the surface of a silicon wafer, referred to as the substrate. Such devices are defined by alternating regions of P-doped and N-doped silicon, usually arranged vertically on the substrate. In a typical bipolar fabrication process, an NPN transistor may be formed by doping an N.sup.+ region in a P.sup.- substrate. After forming an overlying N-type epitaxial layer, additional P-type and N.sup.+ -type regions are formed above the N.sup.+ region initially formed in the substrate.
Although a seemingly limitless number of configurations exist for forming discrete devices, the above example illustrates a common problem encountered in the fabrication of integrated circuits. After the initial N.sup.+ region was formed in the substrate, it was covered by the epitaxial layer. Since the P-type and N.sup.+ -type regions in the epitaxial layer should be vertically aligned with the "buried" N.sup.+ region in the substrate, it is necessary to provide some means for properly locating the masks used for forming the overlying regions. One common approach has been to mark the location of a particular buried region by oxidizing the region to form a recess or indentation. The indentation formed in the substrate will be visible in the epitaxial layer and allows proper alignment of the masks which are used to define doped regions therein.
Although generally functional, the above-described technique for locating the buried regions and aligning the masks, suffers from certain drawbacks. In particular, the uneven surface of the substrate which results from the formation of such indentations interferes with subsequent fabrication steps. For example, natural pattern shift (translation of the indentation) necessitates that components be formed on uneven surfaces (if the area required to construct the component is minimum consistent with other requirements, e.g., breakdown). Transistors formed with active areas overlying the recessed regions will have less than optimum gain characteristics. Component matching will be less than optimum when one component overlies a recess and the other does not. As a final example, forming metallization layers becomes more difficult and breakage of metal interconnect lines becomes more common. The problem is exacerbated as the density of the integrated circuit increases. As devices are formed at increasing density, the maximum line width that can be utilized decreases correspondingly. Such thin interconnect lines are very fragile and particularly susceptible to breakage and failure.
The present invention provides a method for marking the surface of a semiconductor substrate without the need of forming indentations in the active regions of the substrate. By providing a substantially flat surface upon which subsequent layers are deposited, the problems experienced by the prior art which result from an uneven surface on the semiconductor substrate can be avoided. In particular, the problems encountered in forming fragile metallization layers can be reduced or eliminated.